In conventional wafer-level packages, input-output terminals are located over the chip surface area, limiting the number of possible input-output connections. Fan-out wafer level packages (FOWLP) conventionally have a smaller package footprint with greater input-output connections, compared to standard wafer-level packages (WLPs), thereby providing a higher integration level and also a higher number of external electrical contacts.
Conventional fan-out wafer level packages embed each individual die in a low cost epoxy mold compound (EMC) with space allotted between each die for additional input-output points. Redistribution layers (RDLs) are then formed to “fan out” the input-output connections using physical vapor deposition (PVD) seeding, electroplating, and patterning to reroute the input-output connections on the die to the periphery of the epoxy mold compound.
These conventional fan-out wafer level packages require a bumped die (e.g., solder balls), and package-on-package vias that are drilled, plated, etched, or preformed. The fan-out packages demand good alignment between die pads and vias due to die shift, and achieving good alignment can add to the cost.